1. Field of the Disclosure
The disclosure generally relates to a method for forming a gate electrode in a non-volatile memory device, and more specifically, to a method for forming a gate electrode in a non-volatile memory device in which it can prevent undercuts from being formed in a control gate in a process of etching the gate electrode for defining the gate electrode
2. Brief Description of Related Technology
A non-volatile memory device (NVM), such as EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory) and a flash memory, usually includes a gate electrode in which two electrodes are stacked. Generally, the electrode disposed at a lower layer is called a ‘floating gate’ and the electrode disposed at an upper layer is called a ‘control gate’. Furthermore, an Inter-Poly Oxide (IPO) film (hereinafter, referred to as ‘dielectric film’) for enabling programmed electrons to be stored in the floating gate is intervened between the floating gate and the control gate.
A method for forming the gate electrode of the non-volatile memory device constructed above will now be described with reference to FIGS. 9 and 10. FIGS. 9 and 10 are cross-sectional views for explaining the method for forming the gate electrode of the non-volatile memory device in a prior art. Referring to FIGS. 9 and 10, a tunnel oxide film 11, a floating gate 12, a dielectric film 13, a control gate 14, a tungsten silicide layer 15 and a hard mask 16 are sequentially deposited on a semiconductor substrate 10. An etch process using a mask for gate electrode pattern is then performed to firstly pattern the hard mask 16. The mask for gate electrode pattern is removed. Thereafter, an etch process using the patterned hard mask 16 as an etch mask is performed to sequentially pattern the tungsten silicide layer 15, the control gate 14, the dielectric film 13, the floating gate 12 and the tunnel oxide film 11.
However, in the process of patterning the gate electrode, when the dielectric film 13 and the floating gate 12 are patterned after the control gate 14 is patterned, undercuts (see ‘A’ in FIG. 10) are generated in the control gate 14. The reason why the undercuts are generated in the control gate 14 is that the sidewalls of the control gate 14 are damaged by an etch gas when the dielectric film 13 and the floating gate 12 are patterned. If the undercuts are generated in the control gate 14 as such, the Critical Dimension ratio C/B of the gate electrode reduces.
Accordingly, in a process of oxidizing the gate electrode which is performed so as to compensate portions damaged after the gate electrode is patterned, a smiling phenomenon is severely generated in the dielectric film 13. Thus, there occurs a phenomenon that a thickness of the dielectric film 13 increases. In this time, the critical dimension ratio C/B of the gate electrode is the ratio of the critical dimension C of the control gate to the critical dimension B of the floating gate. Accordingly, there occurs a problem in that the program speed is slowed in view of device characteristic.